1. Field of the Invention
The present invention relates to a coating/developing apparatus for performing a coating process of a resist liquid and a developing process after light exposure, on a substrate, such as a semiconductor wafer or an LCD substrate (a glass substrate for a liquid crystal display). The present invention also relates to an operation method and a storage medium used for the apparatus.
2. Description of the Related Art
In order to form a desired resist pattern on a substrate, such as a semiconductor wafer or LCD substrate, a resist liquid is applied onto the substrate to form a resist film, then the resist film is subjected to a light exposure process using a photo mask and a subsequent developing process. Such a series of processes are performed in a system including a coating/developing apparatus for performing resist liquid coating and development and a light exposure apparatus connected to the coating/developing apparatus.
The coating/developing apparatus includes a carrier block, a process block, and an interface block arrayed in a row. The carrier block is configured to place wafer cassettes thereon and includes a transfer arm for transferring semiconductor wafers (which may be referred to as wafers) to and from the wafer cassettes. The process block is configured to perform resist coating and developing processes and so forth on wafers. The interface block is connected to a light exposure apparatus.
After a resist pattern is formed on a substrate, predetermined examinations are performed on the substrate in terms of, e.g., the line width of the resist pattern, the overlapping state between the resist pattern and underlying pattern, and development defects. Then, only acceptable substrates as a result of the examinations are sent to the subsequent steps. These examinations may be performed in stand-alone examination units disposed independently of the coating/developing apparatus. However, it is convenient to adopt an in-line system including the coating/developing apparatus and examination units disposed in the apparatus.
In light of this, Jpn. Pat. Appln. KOKAI Publication No. 2005-175052 (see paragraph number [0042] and FIG. 4) discloses a system that includes an examination block interposed between a carrier block and a process block and provided with a plurality of examination units and a transfer arm. The system disclosed in this document is preset to perform transfer control called restart control in which substrates are transferred from the carrier block through the examination block into the process block, then the processed substrates are once returned into a carrier inside the carrier block, and then the substrates are transferred into the examination block and subjected to examinations.
FIG. 10 is a plan view schematically showing a coating/developing apparatus for performing the transfer control described above, which includes a carrier block 11, an examination block 12, a process block 13, and interface block 14 connected to a light exposure apparatus. FIG. 10 further shows wafer carriers 10, a transfer arm 15 disposed in the carrier block 11, and a transfer arm 16 disposed in the examination block 12. Transfer stages TRS1, TRS2, TRS3, and TRS4 and examination modules IM1, IM2, and IM3 are shown as being arrayed in the plan view for the sake of convenience, but the transfer stages are stacked one on top of the other to form a four-level structure and the examination modules are also stacked one on top of the other to form a three-level structure, for example.
In the coating/developing apparatus shown in FIG. 10, each wafer stored in a carrier 10 is transferred through a route of “transfer arm 15→TRS1→transfer arm 16→process block 13”, so that the wafer is subjected to various processes necessary for resist coating performed by respective modules in the process block 13. Thereafter, the wafer is transferred from the interface block 14 to the light exposure apparatus. Then, the wafer is returned to the process block 13, and is subjected to various processes necessary for a developing process performed by respective modules. Thereafter, the wafer is transferred through a route of “transfer arm 16→TRS2→transfer arm 15” back into a carrier 10.
The wafers stored in the carrier 10 are preset to have a particular order for receiving processes such that, where 25 wafers are stored in the carrier 10, for example, they have serial numbers of No. 1to No. 25assigned thereto. The wafers are transferred into the process block 13 in this order from the lowest substrate number, and are then transferred through predetermined modules in the order. The process block 13 includes transfer arms (main arms) 17A and 17B that perform a cycle transfer to transfer wafers in the order while they are sequentially and cyclically moving among a series of predetermined modules.
On the other hand, after the wafers are returned to the carrier 10, all of or selected part of the wafers are transferred by the transfer arm 15 to the transfer stage TRS3, and are then transferred by the transfer arm 16 to the examination modules. For example, the wafers may include ones to be examined only by the examination module IM1, ones to be examined only by the examination module IM2, ones to be examined only by the examination module IM3, or ones to be examined by the examination module IM1 and then by the examination module IM2. After the wafers are examined by the examination modules IM1 to IM3, they are returned through the transfer stage TRS4 into the carrier 10. In other words, this transfer control is arranged to employ a so-called parallel transfer operation, in which a transfer (production flow) of wafers for performing the coating and developing processes and a transfer (examination flow) for performing the examinations are performed in parallel.
As described above, the examination modules IM1 to IM3 are configured to perform different examinations, and thus time periods necessary for the examinations differ from each other in general. Accordingly, even where wafers are loaded into the examination modules IM1 to IM3 at different timings, the examinations of the examination modules IM1 to IM3 may be finished at almost the same time. In this case, according to the restart control transfer described above, wafers need to wait for their turn to be transferred into the transfer stage TRS4, at the respective examination modules where the wafers have been examined, by a time period not less than one cycle time (the time necessary for the main arms 17A and 17B to circulate the transfer passage), and so the wafers cannot be smoothly unloaded from the examination modules IM1 to IM3. Further, where a wafer is waiting for its turn to be transferred into the transfer stage TRS4 after the examination, a new wafer cannot be loaded into this examination module IM. Accordingly, a delay in transfer into the examination module IM is caused, and thereby increases a time period in which the examination module IM is not used to examine a wafer. In other word, the examination module IM decreases its productivity, and the throughput is thereby lowered.
As a countermeasure against this problem, the number of transfer stages TRS disposed in the examination block 12 may be increased. However, in general, since the space within the examination block 12 is restricted, the number of transfer stages TRS to be disposed in the examination block 12 is limited, and so this countermeasure is not practical.
In the explanation described above, wafers are transferred from one carrier 10 to perform coating and developing processes thereon, then wafers are once returned into the carrier 10, and then the wafers are transferred to examination modules IM to perform examinations thereon. However, studies have been made to develop methods for effectively utilizing the examination modules IM in the examination block 12 while wafers are transferred from one carrier 10 to perform coating and developing processes thereon, as described above. In a method of this kind, in addition to the carrier 10, another or second carrier storing wafers to be only examined is placed in the carrier block 11, and each wafer stored in the second carrier is transferred through a route of “second carrier→TRS3→one or more examination modules IM→TRS4→second carrier”. However, also in this case, since a plurality of examination modules IM are used, transfer of wafers to TRS4 may be retarded and the throughput is thereby lowered, depending on the timings when the examinations of the examination modules IM are finished.